A Novel approach towards performance analysis Of Vedic multiplier using FPGA ’ s

This Paper proposes the implementation of multiplier using ancient Indian vedic mathematics (Urdhvatiryagbhyam) that has been modified to improve performance of high speed mathematics, it shows the modified architecture for a 16*16 Vedic multiplier module using Urdhvatiryagbhyam technique. The design implementation is described in both at gate level and high level RTL code using Verilog Hardware Discription Language. The design is Simulated and Implemented using Xilinx ISE 11.1 Simulator, Xilinx Family: Vertex 2P, Device: XC5VLX30, Speed Grade: -7 and Xilinx Family: Spartan 3AN, Device: XC3S50A, Speed grade: -5 Keywords— Multiplier, Spartan 3AN, Virtex, Urdhva-tiryagbhyam